Receive and Transmit operating modes and command
| START_STOP_RX | When this bit is set the Receive process is placed in the Running state. The DMA attempts to acquire the descriptor from the Receive list and processes the incoming frames.When this bit is cleared the Rx DMA operation is stopped after the transfer of the current frame. |
| OPT_SECOND_FRAME | When this bit is set it instructs the DMA to process the second frame of the Transmit data even before the status for the first frame is obtained. |
| RX_THRESH_CTRL | These two bits control the threshold level of the MTL Receive FIFO. Transfer (request) to DMA starts when the frame size within the MTL Receive FIFO is larger than the threshold. 2’b00: 64， 2’b01: 32， 2’b10: 96， 2’b11: 128 . |
| DROP_GFRM | When set the MAC drops the received giant frames in the Rx FIFO that is frames that are larger than the computed giant frame limit. |
| FWD_UNDER_GF | When set the Rx FIFO forwards Undersized frames (that is frames with no Error and length less than 64 bytes) including pad-bytes and CRC. |
| FWD_ERR_FRAME | When this bit is reset the Rx FIFO drops frames with error status (CRC error collision error giant frame watchdog timeout or overflow). |
| START_STOP_TRANSMISSION_COMMAND | When this bit is set transmission is placed in the Running state and the DMA checks the Transmit List at the current position for a frame to be transmitted.When this bit is reset the transmission process is placed in the Stopped state after completing the transmission of the current frame. |
| TX_THRESH_CTRL | These bits control the threshold level of the MTL Transmit FIFO. Transmission starts when the frame size within the MTL Transmit FIFO is larger than the threshold. In addition full frames with a length less than the threshold are also transmitted. These bits are used only when Tx_Str_fwd is reset. 3’b000: 64 3’b001: 128 3’b010: 192 3’b011: 256 3’b100: 40 3’b101: 32 3’b110: 24 3’b111: 16 . |
| FLUSH_TX_FIFO | When this bit is set the transmit FIFO controller logic is reset to its default values and thus all data in the Tx FIFO is lost or flushed. This bit is cleared internally when the flushing operation is complete. |
| TX_STR_FWD | When this bit is set transmission starts when a full frame resides in the MTL Transmit FIFO. When this bit is set the Tx_Thresh_Ctrl values specified in Tx_Thresh_Ctrl are ignored. |
| DIS_FLUSH_RECV_FRAMES | When this bit is set the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers. |
| RX_STORE_FORWARD | When this bit is set the MTL reads a frame from the Rx FIFO only after the complete frame has been written to it. |
| DIS_DROP_TCPIP_ERR_FRAM | When this bit is set the MAC does not drop the frames which only have errors detected by the Receive Checksum engine.When this bit is reset all error frames are dropped if the Fwd_Err_Frame bit is reset. |